Device for parallel data processing as well as a camera system comprising such a device

ABSTRACT

The invention relates to a device for parallel data processing, a DSP. The device according to the invention comprises a processor matrix ( 100 ) in which processors ( 103 ) are arranged in rows ( 101 ) and columns ( 102 ). Furthermore, the device ( 100 ) comprises first and second external data ports ( 107, 108 ). The rows ( 101 ) arranged in a stepwise manner and the columns are arranged in a stepwise manner. The processors ( 103 ) have a first processor data port ( 104 ), which is connected with one of the first external data ports ( 107 ) by means of first essentially straight connection. The processors ( 103 ) further comprise a second processor data port ( 105 ), which is connected with one of the second external data ports ( 108 ) by means of an essentially straight second connection ( 110 ). The first connection ( 107 ) and the second connection ( 108 ) are oriented substantially orthogonal to each other. A problem associated with conventional DSPs is that the connections to and from the processors within the DSP take up large amounts of silicon area. By arranging both rows and columns of the DSP according to the invention in a stepwise manner the connections may be essentially straight, thus minimizing their lengths and thus the surface area occupied.

The invention relates to a device for parallel data processing.

The invention also relates to a camera system comprising such a devicefor parallel data processing.

Parallel data processing devices are generally known. Such devices arealso generally known to be arranged as integrated circuits. They areknown as Digital Signal Processors (DSPs). A field of application ofDSPs is the processing and manipulating of image data obtained by meansof solid-state image sensors.

In such applications the DSP is included in a camera system comprisingoptics for projecting light images on a solid-state image sensor whichconverts the light images into analog electrical signals, a converterfor converting the analog electrical signals into image data in digitalform and said DSP for further data processing among which, for example,quality improvement of images generated by means of these data on forexample monitors. Quality improvement may comprise for example thesuppression of noise such as fixed pattern noise, contrast enhancementor overexposure compensation.

Camera systems as described above are applied for example in CCTV(Closed-Circuit Television) systems, webcams, mobile telephones, videoconference systems and DSCs (Digital Still Cameras), but also inprofessional recording systems as are used for example in televisionstudios.

Solid-state image sensors indicated above mainly comprise a sensormatrix built-up from rows (image lines) and columns of light-sensitiveelements. In this structure incident light images are split up intopicture elements or pixels. The light-sensitive elements convert thelight images pixel by pixel into an electric signal (pixel signal). Theaggregate pixel signals thus contain information of a complete lightimage. For further processing, the pixel signals are converted intodigital data. The aggregate data thus contain the information of acomplete light image but in digital form now.

Solid-state image sensors are customarily produced in Charge CoupledDevice (CCD) IC technology or a Complementary Metal Oxide Semiconductor(CMOS) IC technology. In both cases the pixel signals are formed byelectrical charge packets. For color information sensing, the individuallight-sensitive elements in the sensor matrix are provided with forexample red, green and blue color filters in an alternating pattern. Asa result of the use of a color filter, each light-sensitive element issensitive to only one color. Besides the applications mentioned above, aDSP can be used in such for calculating color values for the lackingcolors by means of an interpolation method based on the data generatedby adjacent light-sensitive elements.

In a customary reading fashion pixel signals coming from thelight-sensitive elements are converted into data row by row (or imageline by image line) in the sensor matrix. It is customary for this datato be intermediately saved in a line memory prior to further processing.Such a line memory or data buffer has room for the data coming from atleast one image line.

Before the image data is converted into a format that is suitable fordisplay, it is generally necessary for the image data to be processed,for example by combining the color information from different pixels. Inthe device which is necessary for this purpose the associated data perpixel is used as well as data of surrounding pixels in the sensormatrix. Identical processes are then carried out with data coming fromever-different pixels. It is thus obvious for these identical processesto be carried out in parallel for different pixels and for theseidentical processes to be carried out by means of a device for paralleldata processing, for example a DSP. It is a generally recognizedadvantage that DSPs require less time for processing the same amount anddissipate less electrical power than other data processors.

The DSP comprises a plurality of processors and a memory or data bufferfor temporary storage of data still to be processed or for temporarystorage of data already processed or for both. The processors of the DSPand the data buffers have data ports for input and output of the data.

A considerable problem with the designing of the DSP is the positioningthe processors relative to each other and relative to the data buffer inan integrated circuit. The mutual positioning has a great influence onthe routing of the connections between the data ports of differentprocessors and the connections between data ports of processors and dataports of data buffers. The parallelism in data processing requires manyconnections. Consequently, these connections largely determine thesurface area necessary for the integrated circuit on the silicon.

It is an object of the invention to provide a device for parallel dataprocessing, the processors being positioned relative to each other andto the data buffer in a manner that results in a minimum surface area.

Said object is achieved by a parallel data processing device asdescribed in the opening paragraph, characterized as defined in claim 1.

An essentially straight connection is understood to be meant as aconnection that is straight and may have minor bends or curves.

The stepwise mutual arranging of the rows and columns in the processormatrix implies that each row or column of the processors is shifted inthe direction of the rows or columns respectively relative to theprevious row or column respectively. The shift for each row or column isthen in the same direction.

By arranging the processors in such manner, there may be madeessentially straight connections between each of the first processordata ports and the corresponding first further data port and betweeneach of the second processor data ports and the corresponding secondfurther data port. An essentially straight connection is the shortestpossible connection that also takes up minimum surface area. Thisachieves a considerable saving on the required surface area.

A further advantage of the device according to the invention is thatconnections, except for essentially straight connections, are placed asclose together as possible, so that a further saving on required surfacearea is achieved.

In lieu of opting for an integrated circuit having a smaller surfacearea there may also be opted for increasing the functionality of thedevice, for example, by more functionality of larger individualprocessors. This offers possibilities of implementing more advancedimage processing algorithms on the same surface area.

The device also lends itself to application on printed circuit boardsPCBs in which the processors are mounted as separate integrated circuitson a PCB and the connections are formed by the metal tracks on the PCB.

International patent application IB 02/01559 describes a device forparallel data processing and a camera system comprising such a device.The camera system comprises a sensor matrix, a data converter and adevice for parallel data processing, a DSP. This DSP comprises a matrixof processors arranged in rows and columns and a series of firstexternal data ports located outside the processor matrix. The rows ofthe matrix are arranged in a stepwise fashion relative to each other.Further, processors in the matrix have a first processor data port whichis connected with one of the first external data ports by means of afirst at least essentially straight connection. A disadvantage of thisDSP is that the columns of the matrix are not arranged in a stepwisefashion relative to each other. As a result it is impossible in theevent a second processor data port is present on processors in thematrix and second external data ports to interconnect them by means of asecond at least essentially straight connection which is at leastessentially perpendicularly oriented on the first connection.

An embodiment of the device according to the invention is characterizedin that the device comprises a first data buffer for data storage, whichdata buffer has first buffer data ports of which at least one isconnected with one of the first external data ports by means of an atleast essentially straight third connection which is a continuation ofthe first connection. An advantage of this embodiment is that also bymaking the connections between the first external data ports of theprocessors and the first buffer data ports of the first data bufferessentially straight, a further saving on required surface area isachieved.

A further embodiment of the device according to the invention ischaracterized in that the first data buffer is split up into twophysically separated parts, a first part of which is positioned near thefirst row of processors in the processor matrix and a second part ofwhich is positioned near the last row of processors in the processormatrix. An advantage of this embodiment is that a further minimizationof the surface area necessary for the connections is obtained.

A further embodiment of the device according to the invention ischaracterized in that the device comprises a second data buffer for datastorage, which has two buffer data ports at least one of which isconnected with one of the second external data ports by means of afourth at least essentially straight connection that is a continuationof the second connection. An advantage of this embodiment is that alsoby making the connections between the second external data ports of theprocessors and the second buffer data ports of the second data bufferessentially straight, a further saving on required surface area isachieved.

A further embodiment of the device according to the invention ischaracterized in that the second buffer is split up into two physicallyseparated parts a first part of which is positioned near the firstcolumn of processors in the processor matrix and a second part of whichis positioned near the last column of processors in the processormatrix. An advantage of this embodiment is that a further minimizationof the surface area necessary for the connections is obtained.

A further embodiment of the device according to the invention ischaracterized in that processors have a first primary processor dataport and a first secondary processor data port, the first primaryprocessor data port being formed by the first processor data port andthe first primary processor data port of at least one of the processorsbeing connected with the first secondary processor data port of anotherprocessor via the first connection. An advantage of this embodiment isthat when at least one of the processors is supplied through thesecondary processor data port with the same data as another processor,only one connection through the primary processor data port is necessaryto connect a plurality of processor data ports with each other and withat least one of the first external data ports.

A further embodiment of the device according to the invention ischaracterized in that processors have a second secondary processor dataport, the primary processor data port being connected for receiving andprocessing a data element from a series of data elements from one of thefirst external data ports and is connected with the second secondaryprocessor data port of the processor that processes the elementpreceding the data element in the series of data elements and is alsoconnected with the first secondary processor data port of the processorthat processes the element succeeding the data element in the series ofdata elements. This embodiment is highly suitable for processing datafrom one image line in which a processor, in addition to the data of onepixel, which data enters through the first primary processor data portalso needs data of adjacent pixels in the image line, the data of whichenters through the first and the second secondary processor data ports,respectively. One and the same connection is used for this purpose tosupply data both to the first primary processor data port of a processorand to the first and second secondary processor data port respectivelyon two other processors. An advantage of sharing connections in this wayis that a further minimization of the surface area for the connectionsis obtained.

A further embodiment of the device according to the invention ischaracterized in that processors have a second primary processor dataport and a third secondary processor data port, the second primaryprocessor data port being formed by the second processor data port andthe second primary processor data port of at least one of the processorsbeing connected with the third secondary processor data port of anotherprocessor via the second connection. An advantage of this embodiment isalso that data can be supplied to the processors column by column or canbe read from the processors, one connection being shared by a pluralityof processor data ports, so that the required number of connections isminimized. This achieves a further saving on required space.

A camera system according to the invention comprises a sensor matrixbuilt up from rows and columns for converting incident electromagneticradiation into pixel signals, means for converting pixel signals intodata and a parallel data processing device according to the invention Anadvantage of the camera system according to the invention is that as aresult of the relatively small surface area that is required forproducing the device for parallel image data processing, the wholecamera system can be produced as a single integrated circuit. It maynevertheless comprise powerful functions for processing recorded imagedata or improving the quality of the image data in one integratedcircuit. This has made for example real time video and implementation ofadvanced computer vision algorithms possible. Such functions can berealized at lower cost with this. In its turn this makes products forthe consumer market possible having for example video conferencingfunctionality or autonomous scene interpretation.

In an embodiment of the camera system according to the invention thesensor matrix comprises a color filter array in which each processor isarranged for processing data from a plurality of columns of the sensormatrix which data contains color information of different colors of thecolor filter matrix. Each light sensitive element of the sensor matrixcomprises a color filter for for example one of the colors red, green orblue. As a result, each light sensitive element becomes sensitive to oneof said colors. Each processor is arranged for processing data fromvarious columns of the sensor matrix, which contains color informationof different colors of the set comprising red, green and blue. Anadvantage of this is that the color information is sensed without eachpixel separately sensing all three color components red, green or blue.The parallel data processing device calculates the lacking colorinformation per pixel.

The invention will now be further described with reference to an exampleof embodiment and the drawing in which:

FIG. 1 shows in a diagram an embodiment of a matrix of processors of adevice according to the invention,

FIG. 2 shows in a diagram a further embodiment of the matrix ofprocessors of a device according to the invention,

FIG. 3 shows in a diagram a further embodiment of the matrix ofprocessors of a device according to the invention,

FIG. 4 shows in a diagram the positioning of buffers in an embodiment ofthe device according to the invention,

FIG. 5 shows in a diagram the positioning of buffers in a furtherembodiment of the invention,

FIG. 6 shows in a diagram an embodiment of a camera system according tothe invention, and

FIG. 7 shows in a diagram a color film matrix for use in an embodimentof a camera system according to the invention.

In these Figures like component parts are denoted by like referencecharacters.

FIG. 1 gives a diagrammatic representation of an embodiment of a matrixof processors 100 of a device for parallel data processing, a DSP,according to the invention. In the processor matrix 100 the processors103 are arranged in rows 101 and columns 102. The rows 101 are mutuallyarranged in a stepwise fashion. This means that each row 101 is shiftedin the same direction and preferably over the same distance relative tothe previous row 101. Also the columns 102 are mutually arranged in astepwise fashion. Each column 102 is thus shifted in the same directionand over the same distance relative to a previous column 102. Theprocessors 103 have a first processor data port 104 and a secondprocessor data port 105. Further, first external data ports 107 andsecond external data ports 108 are present in the periphery representedby the rectangle 106. The external data ports are located outside theprocessor matrix 100. The external data ports are connection points orterminals for electroconductive connections by which the processors 103are connected with other electronic components which either form part ofthe DSP, or are located outside the DSP. The first processor data port104 of a processor 103 is connected with a first external data port 107by means of a straight connection 109. The second processor data port105 is connected with a second external data port by means of a secondstraight connection 110. The second connection 110 is then situatedtransversely to the first connection 109. It is possible to have thefirst connection 109 and the second connection 110 straight because theprocessors 103 are arranged stepwise in staggered fashion both in therow direction and in the column direction.

Designing integrated circuits is done at different levels. A possiblesubdivision comprises the functional level and the layout level. Atfunctional level the individual parts of an integrated circuit aresubdivided into functional blocks among which, in the case of the DSPshown, the processors 103 and their mutual relations. At layout levelthe various functional blocks, processed in library cells, are thenpositioned and interconnected by connections.

A connection, such as the first connection 109 shown in FIG. 1 and thesecond connection 110, comprises at least one in essence rectangularstrip of electroconductive material that is applied during themanufacturing of an integrated circuit in a manner customary in ICtechnology and provides that at least two parts of the integratedcircuit are interconnected electroconductively. A data port, such as thefirst processor data port 104 shown in FIG. 1, second processor dataport 105, first external data port 107 and second external data port108, is the place where a part of an integrated circuit, for example aprocessor 103, makes electroconductive contact with a connection.

A connection is also understood to mean an assembly of a plurality ofconnections as described above, which are interconnectedelectroconductively in a manner customary in IC technology. In theembodiment shown in FIG. 1 the connections are intended for paralleldata transmission which data comprise a plurality of bits and each ofthe connections shown as such therefore comprises a plurality ofadjacent strips as described above which each individually makeelectroconductive contact with the same data ports. Integrated circuits,which are identical at functional level, may show great mutualdifferences at layout level, because library cells are positionedessentially different relative to each other. This results inconnections that are made in an essentially different manner.

A problem for designing at layout level is the mutual positioning of theprocessors 103. The mutual positioning has a great influence on therouting of the connections between the first or second processor dataport 104, 105 respectively and the first or second external data port107 and 108 respectively. This problem occurs all the more because it isgenerally only possible that (arts of) connections mutually form 45 or90-degree angles or multiples thereof. As a result of the parallelism inthe data processing, many connections are necessary. They thereforelargely determine the surface area that the integrated circuit needs tohave on silicon.

According to the invention the processors 103 are positioned relative toeach other in a manner that results in a minimum surface area. Thestraight first and second connections 109, 110 shown in FIG. 1 are theshortest possible connections between the first and second processordata ports 104, 105 respectively and the first and second external dataports 107, 108 respectively. A shortest possible connection is also theconnection that takes up the smallest surface area. This thus achieves asaving on surface area. A further advantage is that the first and secondconnections 109, 110 cannot only be positioned essentially straight butalso as close together as possible, so that a further required saving onsurface area required is achieved.

In lieu of choosing for an integrated circuit with a smaller surfacearea, there may also be selected to provide more functionality on thesame silicon surface area by increasing the functionality of theindividual processors 103. This offers potential to realize moreadvanced image processing algorithms on the same surface area.

It will be evident that the principle defined above does not only lenditself to being applied to integrated circuits, but that it also lendsitself to being applied to printed circuit boards (PCBs) where theprocessors 103 are positioned as individual integrated circuits on thePCB and the first or second connections 109, 110 respectively are formedby the electro-conductive tracks on the PCB.

FIG. 2 gives a diagrammatic representation of a further embodiment ofthe matrix of processors 200 of a parallel data processing device, a DSPaccording to the invention. In the processor matrix 200 the processors203 are arranged in rows 201 and columns 202. The rows 201 are mutuallyarranged in a stepwise fashion. This means that each row 201 is shiftedin the same direction and preferably over the same distance relative tothe previous row 201. Also the columns 202 are mutually arranged in astepwise fashion. So each column 202 is shifted in the same directionand preferably over the same distance relative to a previous column 202.The processors 203 have a first primary processor data port 204, a firstsecondary processor data port 205, a second secondary processor dataport 206 and a second processor data port 207. Furthermore, theperiphery, indicated by the rectangle 208, has first external data ports209 and second external data ports 210. The external data ports arelocated outside the processor matrix 200. The external data ports areconnection points or terminals for electro-conductive connections bywhich the processors 203 are connected with other electronic componentswhich either form part of the DSP or are located outside the DSP.

The first primary processor data port 204 is connected by means of afirst at least essentially straight connection 211 with the firstsecondary processor data port 205 of a second processor 203 and thesecond secondary processor data port 206 of a third data processor 203.At the same time the first primary processor data port 204 is connectedvia the same first connection 211 with one of the first external dataports 209. The second processor data port 207 is connected by means of asecond at least essentially straight connection 212 to a second externaldata port 210. The second connection 212 is then positioned transverselyto the first connection 211. It is possible for the first connection 211and the second connection 212 to be designed straight, because theprocessors 203 are arranged in staggered fashion both in the directionof the rows and in the direction of the columns.

An advantage of this embodiment is that when the same data is to be sentto both the first processor data port 204 and to the first or secondsecondary data port 205, 206 respectively, on two other processors 203,only one first connection 211 is required to make this possible.

When data are processed coming from one image line it is often necessaryfor a processor 203 also to process data from another pixel in additionto the data of a pixel that enters through the first primary processordata port 204. The former data then comes in through the first secondaryprocessor data port 205 or the second secondary processor data port 206.The embodiment shown in FIG. 2 is highly suitable for this purpose sincethe connections 211 can be straight as a result of the positioning ofthe processors 203 in the processor matrix 200.

The embodiment shown in FIG. 2 is pre-eminently suitable for processingdata comprising sequences of data elements. The processors 203 thenprocess one data element from the series of data elements that aresupplied through the first external data ports 209. The first primaryprocessor data port 204 then receives for example a data element N froma first external data port 209. The same processor 203 also receives onthe first secondary processor data port 205 the data element precedingin the series, for example N−1, and on the second secondary processordata port 206 the data element succeeding in the series, for exampleN+1.

FIG. 3 gives a diagrammatic representation of a further embodiment ofthe processor matrix 300 of a device for parallel data processing, aDSP, according to the invention. In the processor matrix 300 theprocessors 303 are arranged in rows 301 and columns 302. The rows 301and columns 302 respectively are mutually arranged in a stepwisefashion. The processors 303 have a first primary processor data port304, a first secondary processor data port 305, a second secondaryprocessor data port 306, a second primary processor data port 307, athird secondary processor data port 308 and a fourth secondary processordata port 309. Further, the periphery, represented by the rectangle 310,has first external data ports 311 and second external data ports 312.The external data ports 311, 312 are situated outside the processormatrix 300. The external data ports are connection points or terminalsfor electroconductive connections by which the processors 303 areconnected with further electronic components, which either form part ofthe DSP or are situated outside the DSP.

The first primary processor data port 304 is connected by means of afirst at least essentially straight connection 313 with the firstsecondary processor data port 305 of a second processor 303 and thesecond secondary processor data port 306 of a third processor. The firstprimary processor data port 304 is also connected by means of the samefirst connection 313 to one of the first external data ports 311. Thesecond primary processor data port 307 is connected by means of a secondat least essentially straight connection 314 with the third secondaryprocessor data port 308 of another processor 303 and the fourthsecondary processor data port 309 of yet another processor. At the sametime the second primary processor data port 307 is connected by means ofthe same second connection 314 with one of the second external dataports 311.

An advantage of this embodiment is that it is for example suitable forprocessing data coming from a plurality of image lines. Data from afirst image line is then applied to the processors 303 in the processormatrix 300 via the first external data ports 311 and the firstconnections 313. Data from a second image line is applied to theprocessors 303 via the second external data ports 312 and the secondconnection 314. Information belonging to the N^(th) picture element fromthe two image lines is received by a processor 303 on the first andsecond primary processor data port 304, 307 respectively. Information ofthe elements (N−1) from the two image lines is received by the processor303 on the first and third secondary processor data port 305, 308respectively. Information from the elements (N+1) from the two imagelines is received by the processor 303 on the second and fourthsecondary processor data port 306, 309 respectively. Since the first andsecond connections 313 and 314 can supply the same data to variousprocessors, the number of connections required is restricted. Since thefirst and second connections 313 and 314 are arranged essentiallystraight, surface area is saved.

FIG. 4 is a diagrammatic representation of the positioning of buffers inan embodiment of the device according to the invention. The processormatrix 400 shown may be one of the processor matrices 100, 200 or 300.The individual processors are not shown. Along the periphery of theprocessor matrix 400 which periphery is shown by the rectangle 401, thefirst external data ports 402 and the second external data ports 403 areshown. The first external data ports 401 are then in the neighborhood ofthe first or last row of processors in the processor matrix 400 and thesecond external data ports 402 in the neighborhood of the first or lastcolumn of processors in the processor matrix 400. Furthermore are showna first data buffer 404 which has first buffer data ports 406, and asecond data buffer 405 which has second buffer data ports 407.

A first at least essentially straight connection 410 connects one of thefirst external data ports 402 with at least one of the processor dataports on at least one of the processors in the processor matrix 400. Asecond at least essentially straight connection 411 connects one of thesecond external data ports 403 with at least one of the processor dataports on at least one of the processors in the processor matrix 400. Thefirst connection may be one of the first connections 109, 211, or 313.The second connection may be one of the second connections 110, 212 or314. The second connection 411 is oriented essentially transversely tothe first connection 410. A third in essence straight connection 408connects one of the first buffer data ports 406 with one of the firstexternal data ports 402. The first connection 410 is a continuation ofthe third connection 406. A fourth in essence straight connection 409connects either of the second buffer data ports 407 with either of thesecond external data ports 403. The second connection 411 is acontinuation of the fourth connection 408.

Buffers are often necessary for storing data intermediately. As a resultof the third and fourth connections 408, 409 being essentially straightas a continuation of the first and second connections 410 and 411respectively, there has been provided that the least possible surfacearea is added to the DSP.

FIG. 5 gives a diagrammatic representation of the positioning of buffersin a further embodiment of the device according to the invention. Theprocessor matrix 500 shown may be one of the processor matrices 100, 200or 300. The individual processors are not shown. Along the periphery ofthe processor matrix 500 shown by the rectangle 501 are shown the firstexternal data ports 506, 507 and the second external data ports 508 and509. The first external data ports 506 are then located in theneighborhood of the first row of processors in the processor matrix 500and the first external data ports 507 in the neighborhood of the lastrow of processors in the processor matrix 500. The second external dataports 508 are located in the neighborhood of the first column ofprocessors in the processor matrix 500 and the second external dataports 509 in the neighborhood of the last column of processors in theprocessor matrix 500. Further are shown a first part 502 and a secondpart 503 of a data buffer which have first data ports 510, 511 and afirst part 504 and a second part 505 of a second data buffer which havesecond buffer data ports 512, 513.

A first at least essentially straight connection 516 connects one of thefirst external data ports 506, 507 with at least one of the processordata ports on at least one of the processors in the processor matrix500. A second at least essentially straight connection 517 connectseither of the second data ports 508, 509 with at least one of theprocessor data ports on at least one of the processors in the processormatrix 500. The first connection may be one of the first connections109, 211 or 313. The second connection may be one of the secondconnections 110, 212, 314. The second connection 517 is essentiallyoriented transversely to the first connection 516. A third essentiallystraight connection 514 connects one of the first buffer data ports 510on the first part 502, or first buffer data ports 511 on the second part503 of the first data buffer with one of the first external data ports506 or 507 respectively. The third connection 514 is a continuation ofthe first connection 506. A fourth essentially straight connection 515connects one of the second buffer data ports 512 on the first part 504and first buffer data ports 513 on the second part 505 of the seconddata buffer with one of the second external data ports 508 and 509respectively. The fourth connection 515 is a continuation of the secondconnection 517.

The splitting of the first data buffer shown in FIG. 5 into a first part502 and a second part 503 and the splitting of the second data bufferinto a first part 504 and a second part 505 is advantageous in that thefirst connections 516 and second connections 517 respectively can beplaced closer together, so that a further saving on required surfacearea is achieved.

FIG. 6 gives a schematic representation of an embodiment of a camerasystem 600 according to the invention. The camera system 600 comprises asensor matrix 601, means for converting pixel signals into data, thedata converter 602, a device for parallel data processing DSP 603. TheDSP 603 comprises a central controller 604 for coordinating tasks fromthe various parts and is for the rest equal to the DSP shown in FIG. 5.The whole camera system 600 is preferably realized in a CMOS technologyin which all the parts are realized in a single integrated circuit. Inan alternative embodiment the various parts are realized in at least twoseparate integrated circuits. An advantage of this is that the sensormatrix 601 can be realized both in CMOS and in CCD technology.

The sensor matrix 601 is formed by rows, the image lines and columns oflight sensitive elements. With this structure incident light images aresubdivided into pixels. The incident light images are converted perpixel into a pixel signal by the light-sensitive elements. The dataconverter 602 comprises at least one analog-to-digital converter (A/Dconverter). It is to be recommended to simultaneously convert pixelsignals from one and the same image line to data. This requires aplurality of A/D converters, it is true, but the requirements for anindividual A/D converter are less stringent, particularly as regards thespeed of conversion. An arrow 605 indicates the path covered by thepixel signals from the sensor matrix 601 to the data converter 602.

From the data converter 602 the data is sent to the DSP 603. An arrow606 shows the path covered by the data from the data converter 602 tothe DSP 603 and further within the DSP 603. In the embodiment shown thedata is distributed over the first part 502 and the second part 503 ofthe first data buffer. Once the data has been processed in theprocessors of the processor matrix 500 it is passed on to the first part504 and the second part 505 of the second data buffer. From here theprocessed data is sent on. This is indicated by the arrow 607.

FIG. 7 gives a diagrammatic representation of the color film matrix 700to be used in an embodiment of a camera system 600 according to theinvention. When this color film matrix is laid over the sensor matrix,each light sensitive element receiving light of a specific color andthus becoming sensitive to this specific color. The pattern shownprovides that each light sensitive element from the sensor matrix 601becomes sensitive to one of the colors red 701, green 702 or blue 703. Arow in the sensor matrix 601 thus contains information of two of saidcolors. The sensor matrix 601 is always read out row by row. The DSP 603processes one color per processing operation. It is thereforeadvantageous to always process data coming from two adjacent columns inthe sensor matrix 601. They always contain information of two differentcolors. If for example a VGA image comprising 480 rows of 640 pixelseach is to be processed row by row, 320 processors are needed.

In an alternative embodiment of the camera system 600 color informationfrom the adjacent pixels in a row together with adjacent pixels in acolumn are used to determine an interpolated color value.

In the examples discussed particularly embodiments of a camera systemare discussed. It will be evident to a man of ordinary skill in the artthat without departing from the scope of the invention the device forparallel data processing according to the invention lends itself tobeing used in many fields of application.

In this respect one may think of, for example, a device for paralleldata processing comprising a plurality of identical processors, each inits own integrated circuit, in which the processors are arranged in amatrix on a PCB and the connection is formed by the conducting wiringpatterns on the PCB.

The device for parallel data processing also lends itself to otherapplications than the image data processing in a line-by-line fashion. Asimilar device can be used in other applications in which series of dataelements are processed in identical or substantially identical manner.

It is further possible to build up a DSP from a plurality of processormatrices. This is advantageous in that the processors in the variousprocessor matrices simultaneously carry out different processes on thesame data. Two processors lying each in a different processor matrix,but in corresponding positions in the processor matrix, are thensupplied with the same data on their processor data ports. Anotheradvantage is that results of processes of the processors in oneprocessor matrix can be exchanged with the processors from anotherprocessor matrix. Alternatively, it is possible in a DSP built up from aplurality of processor matrices to mirror the processor matricesrelative to one another. This may be advantageous for executing severalprocesses.

1. A device for parallel data processing, characterized in that thedevice comprises at least one matrix of processors arranged in rows andcolumns, first additional data ports located outside the matrix andsecond additional data ports located outside the matrix, in which therows are arranged in a stepwise fashion relative to one another, thecolumns are arranged in a stepwise fashion relative to one another,processors have a first processor data port which is connected with oneof the first external data ports by means of a first at least straightconnection, processors have a second processor data port which isconnected with one of the second external data ports by means of asecond at least essentially straight connection, in which the second atleast essentially straight connection is oriented at least essentiallyorthogonal to the first at least essentially straight connection.
 2. Adevice as claimed in claim 1, characterized in that the device comprisesa first data buffer for data storage which buffer has first buffer dataports of which at least one data port is connected with one of the firstexternal data ports by means of an at least essentially straight thirdconnection which is a continuation of the first connection.
 3. A deviceas claimed in claim 2, characterized in that the first data buffer issplit up into two physically separated parts of which a first part ispositioned close to the first row of processors in the processor matrixand a second part is positioned close to the last row of processors inthe processor matrix.
 4. A device as claimed in claim 1, characterizedin that the device comprises a second data buffer for data storage whichhas second buffer data ports, of which buffer data ports at least one isconnected with one of the second external data ports by means of afourth at least essentially straight connection which is a continuationof the second connection.
 5. A device as claimed in claim 4,characterized in that the second data buffer is split up into twophysically separated parts of which a first part is positioned close tothe first column of processors in the processor matrix and a second partis positioned close to the last column of processors in the processormatrix.
 6. A device as claimed in claim 1, characterized in thatprocessors have a first primary processor data port and a firstsecondary processor data port in which the first primary processor dataport is formed by the first processor data port and the first primaryprocessor data port of at least one of the processors is also connectedwith the first secondary processor data port of another processor viathe first connection.
 7. A device as claimed in claim 6, characterizedin that the first primary processor data port and the first secondaryprocessor data port of processors are arranged for receiving data fromone of the first external data ports.
 8. A device as claimed in claim 7,characterized in that the processors are arranged for processing aseries of data elements, in which processors are arranged for processingat least one data element from the series of data elements.
 9. A deviceas claimed in claim 8, characterized in that processors have a secondsecondary processor data port, in which the primary processor data portis connected for receiving a data element to be processed from theseries of data elements from one of the first external data ports and isconnected with the second secondary processor data port of the processorthat processes the element preceding the data element in the series ofdata elements and is also connected with the first secondary processordata port of the processor that processes the data element succeedingthe data element in the series of data elements.
 10. A device as claimedin claim 6, characterized in that processors have a second primaryprocessor data port and a third secondary processor data port, thesecond primary processor data port being formed by the second processordata port, the second primary processor data port of at least one of theprocessors also being connected with the third secondary processor dataport of another processor via the second connection.
 11. A device asclaimed in claim 10, characterized in that the second primary processordata port and the third secondary processor data port is arranged forreceiving data from one of the second external data ports.
 12. A camerasystem comprising a sensor matrix built up from rows and columns forconverting incident electromagnetic radiation into pixel signals, meansfor converting pixel signals into data and a device comprisingprocessors for parallel data processing as claimed in claim
 1. 13. Acamera system as claimed in claim 12, characterized in that the sensormatrix comprises a color filter matrix and in which processors arearranged for processing data from a plurality of elements of the sensormatrix, which data contains color information of various colors of thecolor filter matrix.